Whitepaper: Assertion Synthesis: Enabling Assertion-Based Verification
For Simulation, Formal and Emulation Flows
Progressive, Targeted Verification through Assertions and Functional Coverage Properties
As design complexity grows, it is imperative that an understanding of the design’s structure and intent be infused into the verification process. Regardless of the speed of the simulator, formal engine, or emulator, the verification result is only as good as the specification. Without an adequate specification, the debugging cycle will continue to increase, and design and verification teams will be unable to adequately reduce the risk of chip defects that can cause re-spin costs and schedule overruns.
Assertion-based verification helps design and verification teams using simulation, formal and emulation methodologies accelerate verification sign-off by enhancing the RTL and test specifications to include assertions and functional coverage properties, which are logic statements that define the intended behavior of signals in the design.
The emergence of Assertion Synthesis will allow for true proliferation of assertion-based verification by automating the painful manual process of creating adequate whitebox assertions and functional coverage properties with sufficient capacity to handle complex SoC designs.
With assertion synthesis, the complete design specification becomes both the RTL and the full complement of assertions; any future incorrect usage of the RTL will be caught by the assertion. Assertion synthesis enables a progressive, targeted verification process, allowing design and verification teams to more easily uncover corner case bugs, expose functional coverage holes, and increase verification observability.
Content Overview:
- Current Functional Verification Limitations: Inadequate Specifications
- Assertion-Based Verification: Targeted Verification via Robust Specifications
- Assertion Synthesis as part of Assertion-based Verification Methodology
- Case Study: Assertion Synthesis in a Random Simulation Flow
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